In development of advanced CMOS (complementary MOS) devices wherein transistors have increasingly smaller dimensions, there is the problem of degradation in the driving current due to depletion of a polycrystalline silicon (poly-Si) electrode and increase in the gate leakage current caused by a smaller thickness of the gate insulation film. Thus, a hybrid technology is investigated which can avoid depletion of the gate electrode by application of a metal gate electrode, and at the same time, reduce the gate leakage current by using a higher-permittivity material for the gate insulation film to increase the physical film thickness thereof.
Pure metal, metal nitride, silicide material etc. have been examined as the materials for use in the metal gate electrode. Use of either material requires that:    (1) threshold voltage (Vth) of the N-type MOSFET and P-type MOSFET be set at a suitable value;    (2) degradation scarcely occurs in the gate insulation film upon forming the metal gate electrode; and    (3) resistivity of the gate electrode be lower.
As to the above item (1), in order to achieve a lower-power-consumption device among other advanced CMOS devices, in particular, it is necessary to set the threshold voltage (Vth) of the CMOS transistors configuring the device within a range of ±0.25V and ±0.5V. For achieving this Vth, the gate electrode material configuring the N-type MOSFET should be a material having a work function which is equal to or below the mid gap (4.6 eV) of Si, and preferably between 4.5 eV and 4.3 eV, whereas the gate electrode material configuring the P-type MOSFET should be a material having a work function which is above the mid gap (4.6 eV) of Si, and preferably between 4.7 eV and 4.9 eV.
In view of the above, there is a proposed technique (dual-metal gate technique) as a countermeasure that different metals or alloys having different work functions be used separately for the N-type MOSFET gate electrode and P-type MOSFET gate electrode to control the Vth of the transistors.
As a semiconductor device using the dual-metal gate technique, a first literature (International electron devices meeting technical digest, 2002, p. 35), for example, discloses a semiconductor device wherein gate electrodes configured by Ta and Ru are formed on SiO2. In the first literature, it is described that Ta and Ru have work functions of 4.15 eV and 4.95 eV, respectively, and that a modulation with 0.8 eV onto the work function is possible between both the gate electrodes,
As another example of the semiconductor device using the dual-metal gate technique, there is technique wherein the same high-melting-point metal having an effective work function in the vicinity of the mid gap of silicon, or an alloy thereof is used as the gate electrode material of both-type MOSFETs, and the gate electrodes of the both-type MOSFETs include therein different impurities. In this metal gate technique, different kinds of impurities are added to a portion of the MOSFETs designed for the gate electrodes, and a high-temperature anneal process is subsequently performed, to thereby form different MOSFETs having different effective work functions. The feature of this metal gate technique is that a process similar to that used in the conventional technique can be used only by replacing polycrystalline silicon (polysilicon) by a high-melting-point metal or a silicide thereof.
As a semiconductor device using the above technique, a second literature (International electron devices meeting technical digest 1985, p. 41) and Patent Publication JP-1996-130216A describe that Mo silicide or W silicide including therein silicon (Si) in a content larger than a stoichiometric content is used, and B ions and As ions are implanted into the P-type MOSFET gate electrode and N-type MOSFET gate electrode, respectively, to control the effective work function in a range between 4.2 eV and 5.1 eV.
More recently, a full-silicidation technique for forming the gate electrodes attracts an attention, wherein a polysilicon gate pattern to be configured as the N-type MOSFET gate electrode and P-type MOSFET gate electrode is subjected to complete silicidation using a metal, such as Ni. The feature of this technique is that source/drain regions of the CMOS are formed, then thermally treated for activation of impurities, and thereafter, the polysilicon gate pattern is subjected to silicidation in a self-alignment manner. This allows the process to have a higher consistency with the conventional process.
A third literature (International electron devices meeting technical digest, 2002, p. 24) and a fourth literature (International electron devices meeting technical digest, 2003, p. 31) describe a semiconductor device using the above full-silicidation technology. More specifically, the third and fourth literatures disclose a technique wherein SiO2 is used for the gate insulation film, a polysilicon gate pattern doped with impurities, such as P or B, is used as the gate electrode, which is subjected to complete silicidation using Ni to form Ni-silicide electrodes (P-doped NiSi for the N-type MOSFET gate electrode, and B-doped NiSi for the P-type MOSFET gate electrode), thereby achieving an effective work function modulated with 0.5 eV at a maximum.
A fifth literature (International electron devices meeting technical digest, 2004, p. 91) and Patent Publication WO 2006/001271 disclose a semiconductor device using a higher-permittivity insulation film made of HfSiON as the gate insulation film, as shown in FIG. 2, and using a gate electrode having a Ni-silicide crystal phase that is subjected to the complete silicidation. In this MOSFET, the effective work function is controlled by controlling the crystal phase (composition) of the Ni-silicide (phase-controlled Ni-full-silicidation technique),
FIGS. 5A to 5I show the fabrication process described in WO 2006/001271. This fabrication process first forms source/drain regions 6 for the N-type MOSFET and P-type MOSFET in the semiconductor substrate 2, and a gate pattern 14 made of polysilicon and a mask layer 15 on the semiconductor substrate 2. FIG. 5A shows a top plan view thereof in this state, and FIGS. 5B, 5C and 5D show B-B′ sectional view, C-C′ sectional view and D-D′ sectional view, respectively, taken in FIG. 5A.
Subsequently, an interlayer dielectric film 10 is formed on the entire surface, in the state shown in FIGS. 5A-5D. Thereafter, planarization of the interlayer dielectric film 10 is performed to expose the top portion of the mask layer 15, which is then removed to expose the polysilicon film 14 (FIGS. 5E and 5F).
Subsequently, a Ni film 16 is deposited on the entire surface, followed by providing a Ni-diffusion preventing film 18 on the gate pattern which is to be formed as the N-type MOSFET gate electrode, and depositing another Ni film 16 thereon (FIGS. 5G and 5H). Thereafter, an anneal process is performed for silicidation of the gate pattern 14, thereby forming MOSFET gate electrodes 8 and 9 (FIGS. 5I and 5J). At this stage, the Ni film 16 deposited on the diffusion preventing film 18 on the N-type MOSFET gate pattern 14 does not react with the polysilicon gate pattern, whereas the Ni film 16 deposited on the P-type MOSFET gate pattern 14 can react completely with the polysilicon gate pattern. As a result, the Ni that is deposited on the gate pattern to be formed as the N-type MOSFET gate electrode and the Ni that is deposited on the gate pattern to be formed as the P-type MOSFET gate electrode have different film thicknesses therebetween, whereby it is possible to make the Ni-silicide have different crystal phases.
Use of the above full-silicidation technology attains control of the effective work function in a wide range by providing different contents for the gate electrode material as shown in FIG. 3. It will be understood from FIG. 3 that the effective work function can be modulated in a range of about 0.4 eV by changing the gate electrode material from NiSi2 through NiSi to Ni3Si. More concretely, WO 20061001271 uses Ni3Si as the P-type MOSFET gate electrode material and NiSi2 as the N-type MOSFET gate is electrode material, thereby setting the Vth of the CMOS transistor in a range of ±0.3V.
According to the analysis by the present inventor, there are some problems in the above conventional techniques, as described hereinafter. The dual-metal gate technique such as described in the first literature separately forms the both-type MOSFET gate electrodes to include different metals or alloys having different work functions. This requires etching of the gate pattern deposited on the gate insulation film for removal, to form different gate electrodes for respective types of MOSFET. For example, in order for depositing a metallic material for the N e MOSFET gate electrode after depositing another metallic material for the P-type MOSFET gate electrode on the entire wafer surface, it is necessary to remove by etching the metallic material for the P-type MOSFET gate electrodes already deposited on the N-type MOSFET gate pattern, while leaving the gate insulation film. This may result in degradation in the device characteristic or reliability due to the quality degradation of the gate insulation film occurring upon the etching for removal. In addition, it is difficult to develop an etching technique which has a sufficient etch selectivity for the two metallic materials used for the N-type MOSFET gate electrode and P-type MOSFET gate electrode with respect to the Si substrate, and is capable of patterning both the materials at the same time.
If a gate electrode made of a high-melting-point metal silicide and having a Si content higher than the stoichiometric content thereof, such as disclosed in the second literature and JP-1996-130216A, is used, there may occur diffusion of impurities doped in the gate electrodes toward the outside thereof, or may occur a significant range of variation in the effective work function due to phase separation of the silicide during a high-temperature anneal process for activating the source/drain regions, thereby causing degradation in the reproducibility or uniformity of the devices.
In the technique for modulating the effective work function by using the full silicidation of the polysilicon doped with impurities, such as described in the third and fourth literatures, if the gate insulation film is configured by a high-permittivity film (HfSiON), there is a problem in that a pinning phenomenon of the Fermi level occurring on the poly-Si/HfSiON interface before the full silicidation is not avoided, whereby the effect of modulation of the effective work function by using the impurities cannot be obtained. Thus, there occurs a problem in that the threshold voltage of the MOSFET cannot be set at a suitable value.
In the phase-controlled Ni-full-silicidation technique described in the fifth literature and WO 2006/001271, if the MOSFET gate electrode materials directly contact each other, one of the gate electrode materials diffuses toward the other of the gate electrode materials during the full silicidation (during the anneal), as shown by an arrow in FIG. 6, whereby there may occur a case wherein the composition of the gate electrodes becomes uneven and it is impossible to control the Vth at a desired value.
FIGS. 4A to 4D show an ideal structure in the case where the MOSFET gate electrode materials contact each other and where these gate electrodes are formed by the phase-controlled full-silicidation technique. FIG. 4A shows a top plan view of the semiconductor device. FIGS. 4B, 4C and 4D are B-B′ sectional view, C-C′ sectional view and D-D′ sectional view, respectively, taken in FIG. 4A. If Ni silicides having different crystal phases are formed for the N-type MOSFET and P-type MOSFET gate electrodes by using the phase-controlled Ni-full-silicidation technique, the different crystal phases contact each other on the device isolation area, as shown in FIGS. 4A and 4B, and it is thus necessary to maintain both the crystal phases in a stable state.
However, since the N-type MOSFET and P-type MOSFET gate electrode materials are coupled with each other on the device isolation area, the gate electrode materials diffuse from one of the gate electrodes to the other during forming the MOSFET gate electrodes or the anneal processing performed thereafter, and the composition of the gate electrodes may be deviated from a desired composition.
For example, in the semiconductor device of WO 2006/001271, as shown in FIG. 7, excessive Ni deposited on the P-type MOSFET area diffuses in a lateral direction (direction from the P-type MOSFET gate electrode toward the N-type MOSFET gate electrode: direction of the arrow shown in FIG. 7). Therefore, there occurs a case where the excessive Ni diffuses into a portion of the gate pattern, to be formed as the N-type MOSFET gate electrode, across the device isolation area to thereby silicidate the gate pattern. As a result, a crystal phase same as the crystal phase of the P-type MOSFET gate electrode may be formed in a part of the N-type MOSFET gate electrode, to cause a range of variation in the Vth.
In addition, in those semiconductor devices, there is a case where the gate electrode materials diffuse between the MOSFET gate electrodes due to a post-process heat treatment conducted after forming the gate electrodes, in addition to the above silicidation process. As a result, as shown in FIG. 7, MOSFET gate electrodes have therein an intermediate phase or mixed phases including different phases, thereby causing a range of variation of the Vth.